1. Field of the Invention
The present invention relates to methods for forming high-k dielectric layers, in particular to methods for forming high-k dielectric layers used as gate dielectric in field effect transistors, to high-k dielectric layers so obtained, and to semiconductor devices comprising such high-k dielectric layers.
2. Description of the Related Technology
Nowadays, one of the main microelectronics industry's demands is the increase of the circuit density. This means that devices have to be scaled to continuously smaller dimensions. The shrinking of the field effect transistor feature size necessitates the decrease of the gate dielectric layer thickness that reaches its practical limit with the conventional gate dielectric material, like silicon oxide or silicon oxynitride. Because dielectric layer thicknesses of only a few nanometers are expected to be commonly used in the future, alternative materials have to be considered with which it is possible to still have an EOT (equivalent oxide thickness) of a few nanometer but with a larger physical thickness. These materials, characterized by a higher dielectric constant compared to silicon oxide (k=3.9), have been called high-k dielectric materials. Some examples of these materials are hafnium oxide, tantalum oxide and zirconium oxide, which have a k-value in the range of 20-25.
When using a layer of these high-k dielectric materials in e.g. transistor applications two key requirements are very important:                an extremely high quality of the dielectric-channel interface, and        the layer is able to withstand semiconductor processing conditions after its formation.        
A high-k dielectric layer can be deposited by several techniques, as there are PVD (physical vapor deposition) and CVD (chemical vapor deposition).
When depositing a high-k dielectric layer by CVD, mostly two techniques may be used, namely Atomic Layer Deposition (ALD) and Metal Organic CVD (MOCVD).
ALD is based on subsequent exposure of the substrate surface to precursor gases, for example a metal halide and H2O. In between two precursor pulses, an N2 pulse purges out non-reacted reagents as well as the reaction products. The precursor pulses are long enough in order to saturate the full wafer surface with the precursor molecule in a chemisorption reaction.
The MOCVD reaction is a typical thermally driven system with simultaneous injection of the precursors, typically a metal organic precursor and oxygen.
A major problem is that thin high-k dielectric layers suffer more from electrical leakage than bulk, i.e. thick, high-k dielectric layers.
FIGS. 1a and b show the density (g/cm3) of ALD-deposited HfO2 layer versus number of deposition cycles of the ALD sequence. For reference purposes the values for cubic (C), tetragonal (T) and monoclinic (M) phase of a bulk, i.e. a thick, layer is added in the circle B shown in FIG. 1b. The density of the HfO2 layer was determined using Rutherford Backscattering Spectroscopy (RBS) in combination with Transmission Electron Microscopy (TEM) (squares) or using X-Ray Reflectance (XRR) (diamonds). FIG. 1a shows the density of the ALD-deposited film as a function of the number of deposition cycles during the first 100 deposition cycles. Some of the deposited films were annealed (open symbols), while other deposited films remain as-deposited (solid symbols). FIG. 1b shows the density during the first 1000 deposition cycles. It cannot be seen from the drawings, but a number of 40 cycles corresponds to a layer thickness of about 2 nm, 100 cycles to about 5 nm and 200 cycles to about 10 nm. As shown by the encircled data points B in FIG. 1b, the density value of the bulk phases is about 10 g/cm3. This bulk density value can only be reached with ALD-deposited layers after more than about 200 deposition cycles. For fewer cycles, which means thinner layers, the density of the ALD-deposited layer decreases significantly with decreasing number of cycles, resulting in electrically leaky regions in the high-k dielectric layer. When using such thin high-k dielectric layers, although having electrically leaky regions, as gate dielectric in e.g. semiconductor devices, the electrical performance of the device significantly decreases.
FIG. 2 is a Conductive Atomic Force Microscopy (C-AFM) picture from scanning a 2 nm thick MOCVD hafnium silicate (HfSiOx) layer over 1000 nm. The topography map (top of FIG. 2) is indicative of the layer roughness having a root mean square roughness value (RMS) of 0.175 nm. The current map (bottom of FIG. 2) shows a high amount of black spots, an example being indicated by the arrow, which indicate electrically leaky regions in the layer.
In “High-k materials for advanced gate stack dielectrics: a comparison of ALCVD and MOCVD as deposition technologies”, published in the Proceedings of the Material Research Society Symposium 2003 Vol. 765, Caymax et al report that the density of thin high-k dielectric layers increases with increasing deposition temperature.
FIG. 3 shows the thickness (A) as a function of the ALD deposition temperature. The thickness was determined using an ellipsometric thickness measurement. FIG. 3 shows that for ALD the HfO2 layer thickness decreases with increasing deposition temperature for an equal number of deposition cycles. As the amount of HfO2 deposited per cycle is very similar at all deposition temperatures, this suggests that consequently the density of the ALD deposited layer increases with increasing deposition temperature.
FIG. 4 shows the density (g/cm3) of an MOCVD deposited HfO2 layer as a function of the layer thickness (nm). The thickness of the layer was determined using TEM. The HfO2 layer was deposited at respectively 300° C. (squares), 485° C. (triangles) and 600° C. (circles). FIG. 4 shows that in case of MOCVD the HfO2 layer density also increases with increasing deposition temperature.
However, increasing deposition temperatures lead to a thicker interfacial dielectric layer, e.g. silicon oxide layer, between the high-k dielectric layer and the substrate surface, e.g. silicon substrate surface. FIG. 5 shows the thickness of a silicon oxide interface layer as a function of the deposition time of an MOCVD-deposited HfO2 layer. The HfO2 layer was formed on a silicon substrate which was either covered with 1 nm of silicon oxide formed by Rapid Thermal Oxidation (RTO) (dotted line) (open symbols) or cleaned by HF-dip (solid line) (closed symbols). The layers were deposited at 300° C. (triangles), 485° C. (solid and open circles for cleaned or not cleaned situation respectively) or at 600° C. (squares). In FIG. 5 is shown that after a deposition time of 60 s the silicon oxide interfacial layer under the MOCVD HfO2 layer becomes significantly thicker with increasing deposition temperatures. A thicker interfacial layer results in a decreased k-value of the overall gate dielectric layer as it is a stack of a silicon-oxide layer with a k-value of about 3.9 and a high-k layer. Using a thus formed high-k dielectric layer as gate dielectric layer in e.g. semiconductor devices leads to a deterioration in the electrical performance of the device.
Further it is also known that a post-deposition anneal of the high-k dielectric layer increases the density. However, during this anneal also the thickness of the interfacial layer between the high-k dielectric layer and the substrate surface increases, again resulting in lower k-values.
Hence, there is a need for a method to form high-quality high-k dielectric layers, preferably thin, i.e. in the nanometer range, which can be used as gate dielectric layer in semiconductor devices, e.g. in field effect transistors.